SoC Test: Trends and Recent Standards

The well-known approaching test cost crisis, where semiconductor test costs begin to approach or exceed manufacturing costs has led test engineers to apply new solutions to the problem of testing System-On-Chip (SoC) designs containing multiple IP (Intellectual Property) cores. While it is not yet possible to apply generic test architectures to an IP core within a SoC, the emergence of a number of similar approaches, and the release of new industry standards, such as IEEE 1500 and IEEE 1450.6, may begin to change this situation. This paper looks at these standards and at some techniques currently used by SoC test engineers. An extensive reference list is included, reflecting the purpose of this publication as a review paper

A hardware implementation of a qEEG-based discriminant function for brain injury detection

This paper presents a feature extraction engine based on using Electroencephalogram (EEG) as a tool for Traumatic-Brain-Injury (TBI) detection. The design focuses on the development of hardware accelerator components integrated onto an FPGA platform. Utilizing a combination of four key quantitative-EEG (qEEG) features, the hardware design can perform a discriminant function (DF) based on 20 variables used for predicting TBI. Since the design is intended to operate in real-time and needs to perform intensive EEGprocessing tasks, the emphasis is on the architectural aspects and speed capabilities of the feature extraction work